IInd Semester

Theory 28 Hrs, Assignment 72 Hrs


  • Introduction to Product Development Cycle
  • Conceptualization Phase
  • Product Scope (customer base, competition, revenue, use cases) Requirement and Feasibility Analysis, PoC Identification, Overall solution Architecture (h/w +s/w), 4.Resource Estimation
  • Planning Phase- Product Design, Interface, Design, Project Planning, Test Plan
  • Implementation Phase:
    • Version control, Component Identification, Simulation, Physical realization, Unit Test, Code review. Coding standards, BUG TRACKING, PCR : Product Change request
    • Validation: Function Testing, System Testing, Stress testing, Documentation
    • Embedded Domains and specific care about.

List of Practical/Assignment

  • Assignment on Conceptualization
  • Assignment on Planning Phase
  • Assignment Implementation Phase
  • Assignment on Validation

Theory – 35 Hrs, Practical 75 Hrs


  • Recollection on Pointers
  • Linked list, Hash, Sorting Algos. Structures, packed structures, function pointers
  • Design of Reusable, Portable software, Understand layering, Development Generic reusable components.
  • Understanding S/W Performance Attributes through case studies
  • Understanding S/W security aspects through case studies
  • S/W design for integrated debug and trouble shoot , through case studies
  • Need for Real Time OS, Mapping Windows threads to RTOS threads concepts, RTOS performance metric
  • Synchronization Primitives in RTOS
  • Timer Functionality, CPU load,

List of Practical:

  • Writing Standard data structure and Algos
  • Coding for Performance
  • Coding For Security
  • Develop RTOS based multi-tasking sample application

24 Hrs


  • Product innovation/development process, Validating thoughts/ideas. Steps required for taking an idea from Concept stage to customer satisfactory level.
    • Activity: Role Play
  • Lateral thinking, Mind Mapping Techniques
    • Activity: Mind Mapping Exercise
  • Planning meetings with customer, Capturing customer requirements and pain area.
    • Activity:
    • Case Study
    • Roll Play
  • Leadership qualities, Self-motivation process

Theory – 36 Hrs, Practical – 48 Hrs


  • PLD – Design Flow and Tool introduction
  • Design using Verilog
  • PLD Architecture – CPLD, FPGA
  • Synthesis Issues and Design Optimization
  • Simulation Issues and Test Automation
  • Special PLDs & Applications- DSP, SOC, Communication

List of Practical/Assignments

  • Design & Implement ALU on FPGA kit
  • Design & Implement ADC & DAC interface to FPGA
  • Design & Implement Serial Port (UART) on FPGA and communicate with PC
  • Design and Implement one DSP algorithm on FPGA
  • Students in the group of 3 will design a complete system using one of the FPGA. The stages will be like: Datasheet & Application study, Block diagram, Component selection, Schematic, Modeling in HDL, Simulation
  • Presentation and Group discussion with the class.

Project Stage II

The Second phase of the project will also be continuously evaluated. Evaluation would be done primarily both “how” the project execution was performed (Process Compliance/Quality of Design/..) and “How” complete the product to the product specification.

  • ekLakshya Innovation Labs Pvt Ltd,
    C-Lite Building,
  • BVB Campus Vidyanagar, Hubli
    Hubli Karnataka 580031 India
  • Phone: 0836-2272210 / 8050050183 / 8050050185
  • Email: info@eklakshya.com

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